Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Requirements for models of achievable routing
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Wiring layer assignments with consistent stage delays
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Incorporating Yield Enhancement into the Floorplanning Process
IEEE Transactions on Computers
The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Wire layer geometry optimization using stochastic wire sampling
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
A differential equation for placement analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Determination of Yield Bounds Prior to Routing
DFT '99 Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems
Multi-objective optimization of interconnect geometry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Hierarchical extraction of critical area for shorts in very large ICs
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Hierarchical critical area extraction with the EYE tool
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
The future of interconnection technology
IBM Journal of Research and Development
Multi-objective optimization of interconnect geometry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
TROY: track router with yield-driven wire planning
Proceedings of the 44th annual Design Automation Conference
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
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Functional yield is a term used to describe the percentage of dies on a wafer that are not affected by catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires and cuts, which result in broken wires. Functional yield is therefore determined by the geometry of the routing channels, how these channels are filled with wire and the distribution of defect sizes. Since the wire spacing and width are usually fixed and the distribution of defects within a mature production facility is well known, the problem reduces to estimating individual wire lengths for cuts and to estimating the overlapping distance that two wires share in neighboring sections of the routing grid for bridges. Previous work in this area has analyzed the problem by assuming that all wiring tracks are occupied with wire, leading to overestimates for the probability of failure due to both cuts and bridges. This paper utilizes statistical models of the placement/routing process to provide a more realistic approach for cut and bridge yield estimation. A comparison of the predicted probability of failure within each wiring layer with postlayout data indicate an average error of 20% for cuts and 26% for bridges.