The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
Stochastic wire length sampling for cycle time estimation
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Genetic Algorithms in Search, Optimization and Machine Learning
Genetic Algorithms in Search, Optimization and Machine Learning
Multi-objective optimization of interconnect geometry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Stochastic wire length sampling for cycle time estimation
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Prelayout interconnect yield prediction
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
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The variation of in-plane interconnect geometry (pitch and width) as a function of wiring level results in improved system level performance because the properties of each wiring layer may be tailored to the characteristic lengths of the wires allocated to it. Performance metrics such as interconnect functional yield, and power dissipation are well suited to layer-by-layer optimization since they are determined by geometrical properties integrated across the wiring layer. The cycle time of a circuit, on the other hand, is a poor candidate for geometry optimization because it may be determined by a single wire length allocated to a single wiring layer. This paper addresses this issue by combining a genetic algorithm for geometry optimization with stochastic sampling of the wires lengths used in determining the signal delay within a key circuit block. We present results on how the stability of the optimal cycle time geometries vary as a function of the stochastic variations inherent in the layout process.