Design for testability view on placement and routing
EURO-DAC '92 Proceedings of the conference on European design automation
Cost of silicon viewed from VLSI design perspective
DAC '94 Proceedings of the 31st annual Design Automation Conference
An Interactive Yield Estimator as a VLSI CAD Tool
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Modeling of integrated circuit defect sensitivities
IBM Journal of Research and Development
Yield modeling and BEOL fundamentals
Proceedings of the 2001 international workshop on System-level interconnect prediction
Hierarchical extraction of critical area for shorts in very large ICs
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
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This paper describes the AFFCCA (Accurate, Fast, Flexible Computation of Critical Area) tool. The algorithms implemented in AFFCCA can handle arbitrary geometry, defects causing shorts of arbitrary shapes, and a spectrum of process induced layout deformations. The presented results indicate that the unique features of AFFCCA allow for significant improvements in the accuracy of critical area computations.