Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Requirements for models of achievable routing
ISPD '00 Proceedings of the 2000 international symposium on Physical design
Wiring layer assignments with consistent stage delays
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
Cost based tradeoff analysis of standard cell designs
SLIP '00 Proceedings of the 2000 international workshop on System-level interconnect prediction
The interpretation and application of Rent's rule
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on system-level interconnect prediction
The Effect of Placement on Yield for Standard Cell Designs
DFT '00 Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
Hierarchical extraction of critical area for shorts in very large ICs
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Hierarchical critical area extraction with the EYE tool
DFT '95 Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems
Yield model for fault clusters within integrated circuits
IBM Journal of Research and Development
The future of interconnection technology
IBM Journal of Research and Development
A probabilistic approach to clock cycle prediction
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Prediction of interconnect pattern density distribution: derivation, validation, and applications
Proceedings of the 2003 international workshop on System-level interconnect prediction
Multi-objective optimization of interconnect geometry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Prediction of interconnect adjacency distribution: derivation, validation, and applications
Proceedings of the 2004 international workshop on System level interconnect prediction
Stochastic interconnect layout sensitivity model
Proceedings of the 2007 international workshop on System level interconnect prediction
A Layout Sensitivity Model for Estimating Electromigration-vulnerable Narrow Interconnects
Journal of Electronic Testing: Theory and Applications
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Functional yield is a term used to describe the percentage of dies on a wafer that fail due to catastrophic defects. Within the interconnect these defects are usually caused by particle contamination and are divided into bridging defects, which join adjacent wires, and cuts, which result in broken wires. The probability of failure is therefore determined by the geometry of the routing channels and the distribution of defect sizes. Since the wire spacing and width are usually fixed, and the distribution of defects within a mature production facility is well known, the problem reduces to estimating individual wire lengths for cuts, and to estimating the overlapping distance that two wires share in neighboring sections of the routing grid for bridges. Since the probability of failure is determined by the behavior of the wires averaged over the entire interconnect, the application of System Level Interconnect Prediction (SLIP) techniques is particularly appropriate. This paper presents a method for utilizing previously developed techniques for wire length estimation and layer assignment and applies them to the problem of cut and bridge functional yield estimation.