PALACE: A Parallel and Hierarchical Layout Analyzer and Circuit Extractor

Authors:
Frank Scherber;Erich Barke;Wolfgang Meier
Affiliations:
Department of Electrical Engineering, University of Hanover, Hanover, Germany;Department of Electrical Engineering, University of Hanover, Hanover, Germany;Corporate Research and Development, Siemens AG, Munich, Germany
Venue:
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Year:
1996

Citing 5
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Abstract

Layout verification of VLSI circuits can be speeded up significantly by parallel execution. The approach described in this paper combines parallel and hierarchical verification of cells and cell areas using geometrical partitioning. In contrast to earlier approaches, design rule check and netlist extraction are performed in parallel without any functional restriction. This is accomplished by a new concept called multiple execution switching. Thus, industrial leading edge VLSI circuits can be handled. High speedups are obtained for large real-world layouts. A productive use is possible and will reduce time-to-market considerably.