Post-Layout Verification of the WE DSP32 Digital Signal Processor

Authors:
Laurence E. Bays;Chin-Fu Chen;Evelyn M. Fields;Renato N. Gadenz;W. Patrick Hays;Howard S. Moscovitz;Thomas G. Szymanski
Affiliations:
-;-;-;-;-;-;-
Venue:
IEEE Design & Test
Year:
1989

Citing 3
Cited 2

Space efficient algorithms for VLSI artwork analysis

DAC '83 Proceedings of the 20th Design Automation Conference
The second generation motis mixed-mode simulator

DAC '84 Proceedings of the 21st Design Automation Conference
Synchronous path analysis in MOS circuit simulator

DAC '82 Proceedings of the 19th Design Automation Conference

Circuit extraction on a message-based multiprocessor

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Algorithms for fast, memory efficient switch-level fault simulation

DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference

Quantified Score

Hi-index	0.00

Visualization

Abstract

The authors describe the successful postlayout verification of the WE DSP32 digital signal processor and the application of advanced CAD (computer-aided design) tools. The development work culminated in the smooth transfer of the DSP32 design into high-volume production. During this period, the authors were able to diagnose and repair hundreds of design errors. They also caught errors in the test-vector software and fixed them before first silicon. They estimate that their verification work saved the DSP32 project a year of silicon debugging. In addition, the authors were able to enhance the CAD tools themselves.