DAC '98 Proceedings of the 35th annual Design Automation Conference
Figures of merit to characterize the importance of on-chip inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On-chip inductance modeling and analysis
Proceedings of the 37th Annual Design Automation Conference
Min/max on-chip inductance models and delay metrics
Proceedings of the 38th annual Design Automation Conference
A delay metric for RC circuits based on the Weibull distribution
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
ISQED '03 Proceedings of the 4th International Symposium on Quality Electronic Design
Harmony: static noise analysis of deep submicron digital integrated circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Analysis of on-chip inductance effects for distributed RLC interconnects
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Generation of design guarantees for interconnect matching
Proceedings of the 2006 international workshop on System-level interconnect prediction
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Analog Integrated Circuits and Signal Processing
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The increasing demand for high performance ICs and system on chip necessitates reliable methodologies for reducing pessimism in chip design. In this paper, we investigate how the frequency dependence of loop self inductance affects the RLC delay. We show that the pessimism in the estimation of RLC propagation delay could be as high as 30% if the frequency dependence of inductance is not considered properly. As a means of efficiently computing less pessimistic RLC delay values, we present an analytical model of frequency dependent loop self inductance that can be applied to model a wide range of real design scenarios. We demonstrate that our approach is computationally efficient and produces accurate and realistic (less pessimistic) delay values that lead to significantly improved system performance.