Fast simulation of VLSI interconnects

  • Authors:
  • J. Jain;Cheng-Kok Koh;V. Balakrishnan

  • Affiliations:
  • Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA;Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA;Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA

  • Venue:
  • Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
  • Year:
  • 2004

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Abstract

This work introduces an efficient and accurate interconnect simulation technique. A new formulation for typical VLSI interconnect structures is proposed which, in addition to providing a compact set of modeling equations, also offers a potential for exploiting sparsity at the simulation level. Simulations show that our approach can achieve 50 /spl times/ improvement in computation time and memory over INDUCTWISE (which in turn has been shown to be 400 /spl times/ faster than SPICE) while preserving simulation accuracy.