Efficient inductance extraction via windowing
Proceedings of the conference on Design, automation and test in Europe
KSim: a stable and efficient RKC simulator for capturing on-chip inductance effect
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
How to efficiently capture on-chip inductance effects: introducing a new circuit element K
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
INDUCTWISE: inductance-wise interconnect simulator and extractor
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
On-chip interconnect modeling by wire duplication
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Error bounds for capacitance extraction via window techniques
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Return-limited inductances: a practical approach to on-chip inductance extraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fast simulation of VLSI interconnects
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
| Hi-index | 0.00 |
The determination of the set (or window) of segments that are inductively coupled to a significant degree with a given segment plays a fundamental role in window-based techniques for the extraction of the susceptance of interconnect structures. We present a measure that quantifies the degree of coupling between segments in a window, thereby paving the way for an adaptive scheme for determining the coupling window associated with each segment. This measure has the properties that: (i)~it is well-correlated with the simulation error that is inherent in window-based susceptance extraction techniques, and (ii)~it can be computed efficiently using incremental and computation reuse techniques.