Generating sparse partial inductance matrices with guaranteed stability
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Electromagnetic parasitic extraction via a multipole method with hierarchical refinement
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Inductance 101: modeling and extraction
Proceedings of the 38th annual Design Automation Conference
How to efficiently capture on-chip inductance effects: introducing a new circuit element K
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Hierarchical interconnect circuit models
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
A local circuit topology for inductive parasitics
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Vector potential equivalent circuit based on PEEC inversion
Proceedings of the 40th annual Design Automation Conference
Return-limited inductances: a practical approach to on-chip inductance extraction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Modeling inductive effects accurately and efficiently is a critical necessity for design verification of high performance integrated systems. While several techniques have been suggested to address this problem, they are mostly based on sparsification schemes for the L or L-inverse matrix. In this paper, we introduce CHIME, a methodology for non-local inductance modeling and simulation. CHIME is based on a hierarchical model of inductance that accounts for all inductive couplings at a linear cost, without requiring any window size assumptions for sparsification. The efficacy of our approach stems from representing the mutual inductive couplings at various levels of hierarchy, rather than discarding some of them. A prototype implementation demonstrates orders of magnitude speedup over a full, flat model and significant accuracy improvements over a truncated model. Importantly, this hierarchical circuit simulation capability produces a solution that is as accurate as the hierarchically extracted circuits, thereby providing a "golden standard" against which simpler truncation based models can be validated.