ISPD '00 Proceedings of the 2000 international symposium on Physical design
Layout techniques for minimizing on-chip interconnect self inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Interconnect analysis: from 3-D structures to circuit models
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Fast analysis of a large-scale inductive interconnect by block-structure-preserved macromodeling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The goal of this work was to simulate the effect of the finite conductivity of semiconductor substrates on the on-chip coupling inductance and then to investigate the effect of the on-chip coupling inductance on circuit crosstalk. In addition, the limitations of standard approaches for estimating coupling inductance are examined. A method for the reduction of the coupling inductance and its effect on circuit crosstalk is also discussed.