An efficient terminal and model order reduction algorithm

Authors:
Pu Liu;Sheldon X. -D. Tan;Boyuan Yan;Bruce McGaughy
Affiliations:
Department of Electrical Engineering, University of California, Riverside, CA 92521, USA;Department of Electrical Engineering, University of California, Riverside, CA 92521, USA;Department of Electrical Engineering, University of California, Riverside, CA 92521, USA;Cadence Design Systems Inc., San Jose, CA 95134, USA
Venue:
Integration, the VLSI Journal
Year:
2008

Citing 9
Cited 2

A coordinate-transformed Arnoldi algorithm for generating guaranteed stable reduced-order models of RLC circuits

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Model Order Reduction Techniques for Linear Systems with Large Numbers of Terminals

Proceedings of the conference on Design, automation and test in Europe - Volume 2
SPRIM: structure-preserving reduced-order interconnect macromodeling

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
An efficient method for terminal reduction of interconnect circuits considering delay variations

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
PRIMA: passive reduced-order interconnect macromodeling algorithm

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Asymptotic waveform evaluation for timing analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Guaranteed passive balancing transformations for model order reduction

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient linear circuit analysis by Pade approximation via the Lanczos process

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Hierarchical Krylov subspace based reduction of large interconnects

Integration, the VLSI Journal
Model order reduction of coupled circuit-device systems

International Journal of Numerical Modelling: Electronic Networks, Devices and Fields

Quantified Score

Hi-index	0.00

Visualization

Abstract

The paper proposes an efficient terminal and model order reduction method for compact modeling of interconnect circuits with many terminals. The new method is inspired by the recently proposed terminal reduction method, SVDMOR [P. Feldmann, F. Liu, Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals, in: Proceedings of the International Conference on Computer Aided Design (ICCAD), 2004, pp. 88-92]. But different from SVDMOR, the new method considers higher order moment information for terminal responses during the terminal reduction and separately applies singular value decomposition (SVD) on both input and output terminals for low-rank approximations. This is in contrast to the SVDMOR method where input and output terminal responses are approximated by SVD at the same time, which can lead to large errors when the numbers of inputs and outputs are quite different. We analyze the passivity requirements for SVD-based terminal and model order reduction and show that the combined passive terminal and MOR using SVD method will not lead an effective terminal reduction in general. Our experimental results show that the proposed ESVDMOR method outperforms the SVDMOR method in terms of accuracy for the same reduced model sizes when the numbers of input and output terminals are quite different.