Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Preservation of passivity during RLC network reduction via split congruence transformations
DAC '97 Proceedings of the 34th annual Design Automation Conference
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Compact Reduced Order Modeling for Multiple-Port Interconnects
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Model order reduction of linear networks with massive ports via frequency-dependent port packing
Proceedings of the 43rd annual Design Automation Conference
An efficient terminal and model order reduction algorithm
Integration, the VLSI Journal
Sparse and passive reduction of massively coupled large multiport interconnects
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
DeMOR: decentralized model order reduction of linear networks with massive ports
Proceedings of the 45th annual Design Automation Conference
Hierarchical Krylov subspace based reduction of large interconnects
Integration, the VLSI Journal
Sparse implicit projection (SIP) for reduction of general many-terminal networks
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
On the efficient reduction of complete EM based parametric models
Proceedings of the Conference on Design, Automation and Test in Europe
Proceedings of the 49th Annual Design Automation Conference
Decentralized and passive model order reduction of linear networks with massive ports
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This paper addresses the well known difficulty of applying model order reduction (MOR) to linear circuits with a large number of input-output terminals. Traditional MOR techniques substitute the original large but sparse matrices used in the mathematical modeling of linear circuits by models that approximate the behavior of the circuit at its terminals, and use significantly smaller matrices. Unfortunately these small MOR matrices become dense as the number of terminals increases, thus canceling the benefits of size reduction. The paper introduces a model reduction technique suitable for circuits with numerous terminals. Thetechnique exploits the correlation that almost always exists between circuit responses at different terminals. The correlation is rendered explicit through an SVD-based algorithm and the result is a substantial sparsi.cation of the MOR matrices. The proposed sparsification technique is applicable to a large class of problems encountered in the analysis and design of interconnect in VLSI circuits. Relevant examples are used to analyze and validate the method.