Matrix analysis
DAC '96 Proceedings of the 33rd annual Design Automation Conference
TICER: realizable reduction of extracted RC circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Model Order Reduction Techniques for Linear Systems with Large Numbers of Terminals
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Sparse and efficient reduced order modeling of linear subcircuits with large number of terminals
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Model order reduction of linear networks with massive ports via frequency-dependent port packing
Proceedings of the 43rd annual Design Automation Conference
Direct Methods for Sparse Linear Systems (Fundamentals of Algorithms 2)
Direct Methods for Sparse Linear Systems (Fundamentals of Algorithms 2)
Efficient representation and analysis of power grids
Proceedings of the conference on Design, automation and test in Europe
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Guaranteed passive balancing transformations for model order reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 49th Annual Design Automation Conference
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This paper is concerned with model order reduction of large scale dynamic systems that have sparse matrix representations, particularly systems with large numbers of input/output "ports." We present an algorithm that combines the advantages of widely-used approaches such as PRIMA and TICER but avoids many of the drawbacks of both. The resulting algorithm is capable of highorder rational approximation, exploits network sparsity, preserves passivity, can be extended to general non-symmetric systems, and can be applied to networks with hundreds or thousands of ports. We develop a common mathematical framework that can encompass all three algorithms, show mathematical relations between them, and point out certain special cases where they are equivalent. We show examples from analysis of industrial on-chip RC/RLC networks that demonstrate performance advantages of more than three orders of magnitude.