AWESpice: a general tool for the accurate and efficient simulation of interconnect problems
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Time-domain macromodels of VLSI system interconnects
Time-domain macromodels of VLSI system interconnects
Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Stable and efficient reduction of substrate model networks using congruence transforms
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Partitioning and reduction of RC interconnect networks based on scattering parameter macromodels
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Reduced-order modeling of large passive linear circuits by means of the SYPVL algorithm
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
PRIMA: passive reduced-order interconnect macromodeling algorithm
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Interconnect design for deep submicron ICs
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Projective convolution: RLC model-order reduction using the impulse response
DATE '99 Proceedings of the conference on Design, automation and test in Europe
ENOR: model order reduction of RLC circuits using nodal equations for efficient factorization
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Aggressive crunching of extracted RC netlists
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
Reduced Order Modeling for RLC Interconnect Tree Using Hurwitz Polynomial
Analog Integrated Circuits and Signal Processing
Hurwitz stable reduced order modeling for RLC interconnect trees
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Realizable parasitic reduction using generalized Y-Δ transformation
Proceedings of the 40th annual Design Automation Conference
Realizable RLCK circuit crunching
Proceedings of the 40th annual Design Automation Conference
Branch Merge Reduction of RLCM Networks
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Passive Hierarchical Model Order Reduction and Realization of RLCM Circuits
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Wideband modeling of RF/Analog circuits via hierarchical multi-point model order reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Hierarchical Krylov subspace reduced order modeling of large RLC circuits
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Hierarchical Krylov subspace based reduction of large interconnects
Integration, the VLSI Journal
Sparse implicit projection (SIP) for reduction of general many-terminal networks
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Efficient methods for large resistor networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 49th Annual Design Automation Conference
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TIme Constant Equilibration Reduction (TICER) is a novel RC reduction method tailored for extract/reduce CAD tools. Geometry-minded extraction tools fracture nets into parasitics based on local changes in geometry. The resulting RC circuits can have a huge dynamic range of time-constants; by eliminating the extreme time-constants, TICER produces smaller, less-stiff RC networks. It produces realizable RC circuits; can retain original network topology; scales well to large networks (~107 nodes); preserves dc and ac behavior; handles resistor loops and floating capacitors; has controllable accuracy; operates in linear time on most nets.