Reduced-order modeling of large linear subcircuits via a block Lanczos algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Preservation of passivity during RLC network reduction via split congruence transformations
DAC '97 Proceedings of the 34th annual Design Automation Conference
IES3: a fast integral equation solver for efficient 3-dimensional extraction
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Model Order Reduction Techniques for Linear Systems with Large Numbers of Terminals
Proceedings of the conference on Design, automation and test in Europe - Volume 2
PRIMA: passive reduced-order interconnect macromodeling algorithm
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Stochastic Power Grid Analysis Considering Process Variations
Proceedings of the conference on Design, Automation and Test in Europe - Volume 2
An efficient method for terminal reduction of interconnect circuits considering delay variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Large power grid analysis using domain decomposition
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Proceedings of the 43rd annual Design Automation Conference
Model order reduction of linear networks with massive ports via frequency-dependent port packing
Proceedings of the 43rd annual Design Automation Conference
Off-chip decoupling capacitor allocation for chip package co-design
Proceedings of the 44th annual Design Automation Conference
An efficient terminal and model order reduction algorithm
Integration, the VLSI Journal
Parallel domain decomposition for simulation of large-scale power grids
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Analysis of large clock meshes via harmonic-weighted model order reduction and port sliding
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Hierarchical Krylov subspace reduced order modeling of large RLC circuits
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
DeMOR: decentralized model order reduction of linear networks with massive ports
Proceedings of the 45th annual Design Automation Conference
Hierarchical Krylov subspace based reduction of large interconnects
Integration, the VLSI Journal
Sparse implicit projection (SIP) for reduction of general many-terminal networks
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Allocating power ground vias in 3D ICs for simultaneous power and thermal integrity
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Proceedings of the 49th Annual Design Automation Conference
Model order reduction of coupled circuit-device systems
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields
Fast timing analysis of clock networks considering environmental uncertainty
Integration, the VLSI Journal
Decentralized and passive model order reduction of linear networks with massive ports
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In the process of designing state-of-the art VLSI circuit we often encounter large but highly structured linear subcircuits with large number of terminals. Classical examples are power supply networks, clock distribution networks, large data buses, etc. Various applications would benefit from efficient high level models of such networks. Unfortunately the existing model-order-reduction algorithms are not adapted to handle more than a few tens of terminals. This talk introduces RecMOR, an algorithm for the computation of reduced order models of structured linear circuits with numerous I/O ports. The algorithm exploits certain regularities of the subcircuit response that are typical in numerous applications of interest. When these regularities are present, the normally dense matrix-transfer function of the subcircuit contains sub-blocks that in some sense are significantly low rank and can be compactly modeled by the recently introduced SVDMOR algorithm. The new RecMOR algorithm decomposes the large matrix-transfer function recursively, and applies SVDMOR compression adaptively to the sub-blocks of the transfer function. The result is a reduced order model that is sparse, efficient, and directly usable as an efficient substitute of the subcircuit in circuit simulations. The method is illustrated on several circuit examples.