Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration

Authors:
Zuoyuan Li;Xianlong Hong;Qiang Zhou;Jinian Bian;Hannah H. Yang;Vijay Pitchumani
Affiliations:
Tsinghua University, Beijing, China;Tsinghua University, Beijing, China;Tsinghua University, Beijing, China;Tsinghua University, Beijing, China;Intel, USA, Hillsboro, OR;Intel, USA, Hillsboro, OR
Venue:
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Year:
2006

Citing 15
Cited 4

A matrix synthesis approach to thermal placement

Proceedings of the 1997 international symposium on Physical design
Generic global placement and floorplanning

DAC '98 Proceedings of the 35th annual Design Automation Conference
Interconnect characteristics of 2.5-D system integration scheme

Proceedings of the 2001 international symposium on Physical design
Corner block list: an effective and efficient topological representation of non-slicing floorplan

Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
3D thermal-ADI: an efficient chip-level transient thermal simulator

Proceedings of the 2003 international symposium on Physical design
Partition-driven standard cell thermal placement

Proceedings of the 2003 international symposium on Physical design
3-D Floorplanning: Simulated Annealing and Greedy Placement Methods for Reconfigurable Computing Systems

RSP '99 Proceedings of the Tenth IEEE International Workshop on Rapid System Prototyping
Technology, performance, and computer-aided design of three-dimensional integrated circuits

Proceedings of the 2004 international symposium on Physical design
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Thermal via placement in 3D ICs

Proceedings of the 2005 international symposium on Physical design
A thermal-driven floorplanning algorithm for 3D ICs

Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Thermal-driven multilevel routing for 3-D ICs

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Floorplanning for 3-D VLSI design

Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Cell-level placement for improving substrate thermal distribution

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Estimating routing congestion using probabilistic analysis

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Exploring serial vertical interconnects for 3D ICs

Proceedings of the 46th Annual Design Automation Conference
OPAL: a multi-layer hybrid photonic NoC for 3D ICs

Proceedings of the 16th Asia and South Pacific Design Automation Conference
Assembling 2D blocks into 3D chips

Proceedings of the 2011 international symposium on Physical design
Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture

Journal of Computer and System Sciences

Quantified Score

Hi-index	0.00

Visualization

Abstract

New three-dimensional (3D) floorplanning and thermal via planning algorithms are proposed for thermal optimization in two-stacked die integration. Our contributions include (1) a two-stage design flow for 3D floorplanning, which scales down the enlarged solution space due to multidevice layer structure; (2) an efficient thermal-driven 3D floorplanning algorithm with power distribution constraints; (3) a thermal via planning algorithm considering congestion minimization. Experiments results show that our approach is nine times faster with better solution quality compared to a recent published result. In addition, the thermal via planning approach is proven to be very efficient to eliminate localized hot spots directly.