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ZOMA: A Preemptive Deadlock Recovery Mechanism for Fully Adaptive Routing in Wormhole Networks
ICCNMC '01 Proceedings of the 2001 International Conference on Computer Networks and Mobile Computing (ICCNMC'01)
High-Speed Optoelectronics Receivers in SiGe
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Optical solutions for system-level interconnect
Proceedings of the 2004 international workshop on System level interconnect prediction
Predictions of CMOS compatible on-chip optical interconnect
Proceedings of the 2005 international workshop on System level interconnect prediction
Implementing Caches in a 3D Technology for High Performance Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
3D floorplanning with thermal vias
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
DyXY: a proximity congestion-aware deadlock-free dynamic routing method for network on chip
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Performance Evaluation for Three-Dimensional Networks-On-Chip
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
The case for low-power photonic networks on chip
Proceedings of the 44th annual Design Automation Conference
Interconnects in the third dimension: design challenges for 3D ICs
Proceedings of the 44th annual Design Automation Conference
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Corona: System Implications of Emerging Nanophotonic Technology
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow
Proceedings of the 2nd international conference on Nano-Networks
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
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Proceedings of the 36th annual international symposium on Computer architecture
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NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Exploring serial vertical interconnects for 3D ICs
Proceedings of the 46th Annual Design Automation Conference
Low-Power Reconfigurable Network Architecture for On-Chip Photonic Interconnects
HOTI '09 Proceedings of the 2009 17th IEEE Symposium on High Performance Interconnects
Digital Integrated Circuits
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Proceedings of the Conference on Design, Automation and Test in Europe
Synthesis of low-overhead configurable source routing tables for network interfaces
Proceedings of the Conference on Design, Automation and Test in Europe
ORION 2.0: a fast and accurate NoC power and area model for early-stage design space exploration
Proceedings of the Conference on Design, Automation and Test in Europe
PASTIS: a photonic arbitration with scalable token injection scheme
ACM SIGARCH Computer Architecture News - ACM SIGARCH Computer Architecture News/HEART '12
Co-tuning of a hybrid electronic-optical network for reducing energy consumption in embedded CMPs
Proceedings of the First International Workshop on Many-core Embedded Systems
METEOR: Hybrid photonic ring-mesh network-on-chip for multicore architectures
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
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Three-dimensional integrated circuits (3D ICs) offer a significant opportunity to enhance the performance of emerging chip multiprocessors (CMPs) using high density stacked device integration and shorter through silicon via (TSV) interconnects that can alleviate some of the problems associated with interconnect scaling. In this paper we propose and explore a novel multi-layer hybrid photonic NoC fabric (OPAL) for 3D ICs. Our proposed hybrid photonic 3D NoC combines low cost photonic rings on multiple photonic layers with a 3D mesh NoC in active layers to significantly reduce on-chip communication power dissipation and packet latency. OPAL also supports dynamic reconfiguration to adapt to changing runtime traffic requirements, and uncover further opportunities for reduction in power dissipation. Our experimental results and comparisons with traditional 2D NoCs, 3D NoCs, and previously proposed hybrid photonic NoCs (photonic Torus, Corona, Firefly) indicate a strong motivation for considering OPAL for future 3D ICs as it can provide orders of magnitude reduction in power dissipation and packet latencies.