Technology, performance, and computer-aided design of three-dimensional integrated circuits
Proceedings of the 2004 international symposium on Physical design
Timing, energy, and thermal performance of three-dimensional integrated circuits
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool
Proceedings of the 2005 international workshop on System level interconnect prediction
Implementing Caches in a 3D Technology for High Performance Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
Three-dimensional place and route for FPGAs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
ACM Journal on Emerging Technologies in Computing Systems (JETC)
SSMCB: low-power variation-tolerant source-synchronous multicycle bus
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints
Integration, the VLSI Journal
Error resilience of intra-die and inter-die communication with 3D Spidergon STNoC
Proceedings of the Conference on Design, Automation and Test in Europe
CAD reference flow for 3D via-last integrated circuits
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
ILP-based inter-die routing for 3D ICs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Adaptive inter-layer message routing in 3D networks-on-chip
Microprocessors & Microsystems
Power consumption and performance analysis of 3D NoCs
ACSAC'07 Proceedings of the 12th Asia-Pacific conference on Advances in Computer Systems Architecture
Dynamic Fault-Tolerant three-dimensional cellular genetic algorithms
Journal of Parallel and Distributed Computing
Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture
Journal of Computer and System Sciences
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hree-dimensional integration technologies have beenproposed in order to mitigate design challenges posed bydeep-submicron interconnect. By providing multiple layersof active devices together with high-density local interconnects between these layers,3-D technologies give digital-circuit designers greater freedom in meeting power and delay budgets that are increasingly interconnect-dominated.In this paper, we quantify the benefits 3-D integration canprovide, using specific circuit benchmarks.We perform thisanalysis using a suite of circuit design tools we have developed for 3-D integration. We observe that on average, 28%to 51% reduction in total wire length is possible over twoto five wafers respectively; similarly, 31% to 56% reduction in the length of the longest wire is achievable.We alsocharacterize the impact of technology parameters on thesereductions.