Corner block list: an effective and efficient topological representation of non-slicing floorplan
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Technology, performance, and computer-aided design of three-dimensional integrated circuits
Proceedings of the 2004 international symposium on Physical design
Profile-guided microarchitectural floorplanning for deep submicron processor design
Proceedings of the 41st annual Design Automation Conference
Efficient Thermal Placement of Standard Cells in 3D ICs using a Force Directed Approach
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Thermal via placement in 3D ICs
Proceedings of the 2005 international symposium on Physical design
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Thermal-driven multilevel routing for 3-D ICs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Thermal via planning for 3-D ICs
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Micro-architecture Pipelining Optimization with Throughput-Aware Floorplanning
ASP-DAC '07 Proceedings of the 2007 Asia and South Pacific Design Automation Conference
Efficient Thermal via Planning Approach and Its Application in 3-D Floorplanning
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A novel thermal optimization flow using incremental floorplanning for 3D ICs
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Performance and thermal-aware Steiner routing for 3-D stacked ICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Fixed-outline thermal-aware 3D floorplanning
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Rethinking thermal via planning with timing-power-temperature dependence for 3D ICs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Assembling 2D blocks into 3D chips
Proceedings of the 2011 international symposium on Physical design
Multiobjective optimization of deadspace, a critical resource for 3D-IC integration
Proceedings of the International Conference on Computer-Aided Design
| Hi-index | 0.00 |
Thermal issue is a critical challenge in 3D IC circuit design. Incorporating thermal vias into 3D IC is a promising way to mitigate thermal issues by lowering down the thermal resistances between device layers. However, it is usually difficult to get enough space at target regions to insert thermal vias. In this paper, we propose a novel analytical algorithm to re-allocate white space for 3D ICs to facilitate via insertion. Experimental results show that after reallocating whitespaces, thermal vias and total wirelength could be reduced by 14% and by 2%, respectively. It also shows that whitespace distribution with via planning alone will degrade performance by 9% while performance-aware via planning method can reduce thermal via number by 60% and the performance is kept nearly unchanged.