Technology, performance, and computer-aided design of three-dimensional integrated circuits
Proceedings of the 2004 international symposium on Physical design
Design tools for 3-D integrated circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Exploring compromises among timing, power and temperature in three-dimensional integrated circuits
Proceedings of the 43rd annual Design Automation Conference
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
2.5-Dimensional VLSI system integration
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper, we describe a comprehensive layout methodology for bonded three-dimensional integrated circuits (3D ICs). In bonded 3D integration technology, parts of a circuit are fabricated on different wafers, and then, the wafers are bonded with a glue layer of Cu or polymer based adhesive. Using our layout methodology, designers can layout such 3D circuits with necessary information on inter-wafer via/contact and orientation of each wafer embedded in the layout. We have implemented the layout methodology in 3DMagic. Availability of 3DMagic has led to interesting research with a wide range of layout-specific circuit analyses, from performance comparison of 2D and 3D circuits to layout-specific reliability analyses in 3D circuits. Using 3DMagic, researchers have designed and simulated an 8-bit encryption processor mapped into 2D and 3D FPGA layouts. Moreover, the layout methodology is an essential element of our ongoing research for the framework of a novel Reliability Computer Aided Design tool, ERNI-3D.