Multiplexed switch box architecture in three-dimensional FPGAs to reduce silicon area and improve TSV usage

Authors:
Marzieh Morshedzadeh Morshedzadeh;Ali Jahanian
Affiliations:
Shahid Beheshti University, G. C., Tehran, Iran;Shahid Beheshti University, G. C., Tehran, Iran
Venue:
Proceedings of the great lakes symposium on VLSI
Year:
2012

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Abstract

In this paper, we propose a multiplexed 3D-switch box architecture that decreases the number of TSVs required for routing with a slight overhead in total wirelength. Our experimental results show that the presented architecture reduces the number of routing TSVs by about 48% in cost of less than 2% wirelength overhead.