Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Functional multiple-output decomposition: theory and an implicit algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
RASP: a general logic synthesis system for SRAM-based FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Partially-dependent functional decomposition with applications in FPGA synthesis and mapping
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Journal of the ACM (JACM)
Technology Mapping via Transformations of Function Graphs
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
FPGA Synthesis Using Function Decomposition
ICCS '94 Proceedings of the1994 IEEE International Conference on Computer Design: VLSI in Computer & Processors
An Implicit Algorithm for Support Minimization during Functional Decomposition
EDTC '96 Proceedings of the 1996 European conference on Design and Test
Using Decision Diagrams to Design ULMs for FPGAs
IEEE Transactions on Computers
Technology mapping for FPGAs with nonuniform pin delays and fast interconnections
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
The effect of LUT and cluster size on deep-submicron FPGA performance and density
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Invited talk: synthesis challenges for next-generation high-performance and high-density PLDs
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Interconnect enhancements for a high-speed PLD architecture
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Reconfigurable computing: a survey of systems and software
ACM Computing Surveys (CSUR)
Efficient Decomposition Techniques for FPGAs
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
Efficient Realization of Parity Prediction Functions in FPGAs
Journal of Electronic Testing: Theory and Applications
Area Minimization of Exclusive-OR Intensive Circuits in FPGAs
Journal of Electronic Testing: Theory and Applications
From design to design automation
Proceedings of the 2014 on International symposium on physical design
| Hi-index | 0.00 |
In this paper, we developed Boolean matching techniques for complex programmable logic blocks (PLBs) in LUT-based FPGAs. A complex PLB can not only be used as a K-input LUT, but also can implement some wide functions of more than K variables. We apply previous and develop new functional decomposition methods to match wide functions to PLBs. We can determine exactly whether a given wide function can be implemented with a XC4000 CLB or other three PLB architectures (including the XC5200 CLB). We evaluate functional capabilities of the four PLB architectures on implementing wide functions in MCNC benchmarks. Experiments show that the XC4000 CLB can be used to implement up to 98% of 6-cuts and 88% of 7-cuts in MCNC benchmarks, while two of the other three PLB architectures have a smaller cost in terms of logic capability per silicon area. Our results are useful for designing future logic unit architectures in LUT based FPGAs.