On the Complexity of Mod-2l Sum PLA's
IEEE Transactions on Computers
Boolean matching for complex PLBs in LUT-based FPGAs with application to architecture evaluation
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
IEEE Transactions on Computers
Testing configurable LUT-based FPGA's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fast algorithm to minimize multi-output mixed-polarity generalized Reed-Muller forms
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Logic Synthesis and Optimization
Logic Synthesis and Optimization
A XOR-Tree Based Technique for Constant Testability of Configurable FPGAs
ATS '97 Proceedings of the 6th Asian Test Symposium
A Novel Methodology for Designing TSC Networks Based on the Parity Bit Code
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Reliable Logic Circuits with Byte Error Control Codes: A Feasibility Study
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Logic synthesis of multilevel circuits with concurrent error detection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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This paper presents Exclusive-OR (XOR)-based decomposition methods to implement XOR-intensive circuits efficiently in field programmable gate arrays (FPGAs). The first proposed method is an extension of the Shannon's expansion theorem. Such extension enables us to force decomposing the original circuits into the smaller sub-circuits. The second proposed method is based on the Exclusive-or-Sum-Of-Products (ESOP) expression that transforms AND/OR Boolean functions to AND/XOR functions. The XOR relation enables us to find more efficient grouping for the XOR-intensive circuits. The Microelectronics Center of North Carolina (MCNC) benchmark circuits are used to demonstrate the effectiveness of the proposed techniques. The proposed ESOP expression method is superior to the other common techniques in achieving realization efficiency. The proposed ESOP expression method needs 8.08 extra CLBs on average to implement the parity functions of the MCNC benchmark circuits while the typical method needs 14.31 extra CLBs on average. In other words, when using the proposed ESOP expression method, the number of CLBs is reduced by 34% compared to the typical method.