On the Complexity of Mod-2l Sum PLA's
IEEE Transactions on Computers
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Boolean matching for complex PLBs in LUT-based FPGAs with application to architecture evaluation
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
IEEE Transactions on Computers
Testing configurable LUT-based FPGA's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fast algorithm to minimize multi-output mixed-polarity generalized Reed-Muller forms
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Logic Synthesis and Optimization
Logic Synthesis and Optimization
A Novel Methodology for Designing TSC Networks Based on the Parity Bit Code
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Reliable Logic Circuits with Byte Error Control Codes: A Feasibility Study
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Logic synthesis of multilevel circuits with concurrent error detection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient Realization of Parity Prediction Functions in FPGAs
Journal of Electronic Testing: Theory and Applications
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In this paper, we propose AND/XOR-based decomposition methods to implement parity prediction circuits efficiently in field programmable gate arrays (FPGAs). Due to the fixed size of the programmable blocks in an FPGA, decomposing a circuit into subcircuits with appropriate number of inputs can achieve excellent implementation efficiency. The typical EDA tools deal mainly with AND/OR expressions and therefore are quite inefficient for the parity prediction functions since parity prediction function is inherently based on AND/XOR in nature. The Davio expansion theorem is applied here to the technology mapping method for FPGA. We design three different approaches: (1) Direct Approach, (2) AND/XOR Direct, and (3) Proposed Davio Approach and conduct experiments using MCNC benchmark circuits to demonstrate the effectiveness of Proposed Davio Approach. We formulate the parity prediction circuits for the benchmark circuits. The Proposed Davio Approach is superior to the typical methods for parity prediction circuits in terms of the number of CLBs. The proposed Davio expansion approach, which is basedon AND/XOR expressions, is superior to the other common techniques in achieving realization efficiency. The proposed Davio approach only needs 21 CLBs for eight benchmark circuits. It takes only on average 2.75 CLBs or 20 % of the original area.