On the Complexity of Mod-2l Sum PLA's
IEEE Transactions on Computers
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Boolean matching for complex PLBs in LUT-based FPGAs with application to architecture evaluation
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Methodologies for Tolerating Cell and Interconnect Faults in FPGAs
IEEE Transactions on Computers
Testing configurable LUT-based FPGA's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A fast algorithm to minimize multi-output mixed-polarity generalized Reed-Muller forms
DAC '88 Proceedings of the 25th ACM/IEEE Design Automation Conference
Logic Synthesis and Optimization
Logic Synthesis and Optimization
Efficient Decomposition Techniques for FPGAs
HiPC '02 Proceedings of the 9th International Conference on High Performance Computing
Efficient Parity Prediction in FPGA
DFT '01 Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems
A Novel Methodology for Designing TSC Networks Based on the Parity Bit Code
EDTC '97 Proceedings of the 1997 European conference on Design and Test
Reliable Logic Circuits with Byte Error Control Codes: A Feasibility Study
DFT '96 Proceedings of the 1996 Workshop on Defect and Fault-Tolerance in VLSI Systems
Using Roving STARs for On-Line Testing and Diagnosis of FPGAs in Fault-Tolerant Applications
ITC '99 Proceedings of the 1999 IEEE International Test Conference
Logic synthesis of multilevel circuits with concurrent error detection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Towards a secure and reliable system
EUC'05 Proceedings of the 2005 international conference on Embedded and Ubiquitous Computing
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In this paper, we propose an AND/XOR-based technology mapping method for efficient realization of parity prediction functions in field programmable gate arrays (FPGAs). Due to the fixed size of the programmable blocks in an FPGA, decomposing a circuit into sub-circuits with appropriate number of inputs can achieve an excellent implementation efficiency. Specifically, the proposed technology mapping method is based on Davio expansion theorem. The AND/XOR nature of the proposed method allows it to operate on XOR intensive circuits, such as parity prediction functions, efficiently. We conduct experiments using the parity prediction functions with respect to MCNC benchmark circuits. With the proposed approach, the number of configurable logic blocks (CLBs) is reduced by 67.6% (compared to speed-optimized results) and 57.7% (compared to area-optimized results), respectively. The total equivalent gate counts are reduced by 65.5%, maximum combinational path delay is reduced by 56.7%, and maximum net delay is reduced by 80.5% compared to conventional methods.