Logic synthesis for programmable gate arrays
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
BDD based decomposition of logic functions with application to FPGA synthesis
DAC '93 Proceedings of the 30th international Design Automation Conference
Optimum functional decomposition using encoding
DAC '94 Proceedings of the 31st annual Design Automation Conference
A fully implicit algorithm for exact state minimization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Functional multiple-output decomposition: theory and an implicit algorithm
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
A method for finding good Ashenhurst decompositions and its application to FPGA synthesis
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Lambda set selection in Roth-Karp decomposition for LUT-based FPGA technology mapping
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Compatible class encoding in Roth-Karp decomposition for two-output LUT architecture
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Logic Synthesis and Optimization
Logic Synthesis and Optimization
Combinational logic synthesis for LUT based field programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A Boolean approach to performance-directed technology mapping for LUT-based FPGA designs
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Partially-dependent functional decomposition with applications in FPGA synthesis and mapping
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Boolean matching for complex PLBs in LUT-based FPGAs with application to architecture evaluation
FPGA '98 Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field programmable gate arrays
Compatible class encoding in hyper-function decomposition for FPGA synthesis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Incremental physical resynthesis for timing optimization
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
The effect of post-layout pin permutation on timing
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Computing support-minimal subfunctions during functional decomposition
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Functional decomposition is an important synthesis technique for lookup table based FPGAs. Given a partitioning of a function's input variables into bound set and free set, the extracted subfunctions usually depend on all bound set variables. We show that this, however, is often not necessary. We present an implicit algorithm that finds subfunctions with a minimal support among the huge number of possible subfunctions. Our approach includes non-disjoint decompositions as a special case. The algorithm is very fast due to the use of implicit techniques. Experimental results show substantial area reductions.