PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
Multilevel k-way hypergraph partitioning
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
The effect of LUT and cluster size on deep-submicron FPGA performance and density
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Multi.Objective Hypergraph Partitioning Algorithms for Cut and Maximum Subdomain Degree Minimization
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A new Multilevel Hierarchical MFPGA and its suitable configuration tools
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Performances improvement of FPGA using novel multilevel hierarchical interconnection structure
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
OTIS-MOT: an efficient interconnection network for parallel processing
The Journal of Supercomputing
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In this paper we present a new clustered mesh FPGA architecture where each cluster local interconnect is implemented as an MFPGA tree network [6]. Unlike previous clustered mesh architectures, the mesh of tree allows us to consider large clusters sizes (thanks to MFPGA depopulated local interconnect). Experimentation shows that we obtain a reduction of 14% in switches number and 2 times in the placement and routing run time. Furthermore, compared to MFPGA, the mesh of tree achieves full routability of all MCNC benchmarks since we can easily control both clusters LUTs occupation and mesh channel width.