Multiple-Way Network Partitioning
IEEE Transactions on Computers
A parallel bottom-up clustering algorithm with applications to circuit partitioning in VLSI design
DAC '93 Proceedings of the 30th international Design Automation Conference
Recent directions in netlist partitioning: a survey
Integration, the VLSI Journal
Partitioning similarity graphs: a framework for declustering problems
Information Systems
Multilevel circuit partitioning
DAC '97 Proceedings of the 34th annual Design Automation Conference
The ISPD98 circuit benchmark suite
ISPD '98 Proceedings of the 1998 international symposium on Physical design
On multilevel circuit partitioning
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Multiway partitioning with pairwise movement
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Multilevel hypergraph partitioning: applications in VLSI domain
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Improved algorithms for hypergraph bipartitioning
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Multi-way partitioning using bi-partition heuristics
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Bipartite graph partitioning and data clustering
Proceedings of the tenth international conference on Information and knowledge management
A New Algorithm for Multi-objective Graph Partitioning
Euro-Par '99 Proceedings of the 5th International Euro-Par Conference on Parallel Processing
Multi-objective circuit partitioning for cutsize and path-based delay minimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
An evaluation of bipartitioning techniques
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Enhancing Data Locality by Using Terminal Propagation
HICSS '96 Proceedings of the 29th Hawaii International Conference on System Sciences Volume 1: Software Technology and Architecture
A linear-time heuristic for improving network partitions
DAC '82 Proceedings of the 19th Design Automation Conference
Web Mining: Information and Pattern Discovery on the World Wide Web
ICTAI '97 Proceedings of the 9th International Conference on Tools with Artificial Intelligence
SAT-based optimal hypergraph partitioning with replication
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Crowdedness-balanced multilevel partitioning for uniform resource utilization
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Mesh of Tree: Unifying Mesh and MFPGA for Better Device Performances
NOCS '07 Proceedings of the First International Symposium on Networks-on-Chip
SOC test architecture optimization for signal integrity faults on core-external interconnects
Proceedings of the 44th annual Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An Efficient Approach for Managing Power Consumption Hotspots Distribution on 3D FPGAs
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Interactive image segmentation using probabilistic hypergraphs
Pattern Recognition
Schism: a workload-driven approach to database replication and partitioning
Proceedings of the VLDB Endowment
IR-drop reduction through combinational circuit partitioning
PATMOS'06 Proceedings of the 16th international conference on Integrated Circuit and System Design: power and Timing Modeling, Optimization and Simulation
Adapting biochemical kripke structures for distributed model checking
Transactions on Computational Systems Biology VII
Mining potential research synergies from co-authorship graphs using power graph analysis
International Journal of Web Engineering and Technology
A hybrid partitioning algorithm based on natural mechanisms of decision making
Scientific and Technical Information Processing
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In this paper we present a family of multi-objective hypergraphpartitioning algorithms based on the multilevel paradigm, whichare capable of producing solutions in which both the cut and themaximum subdomain degree are simultaneously minimized. Thistype of partitionings are critical for existing and emerging applications in VLSI CAD as they allow to both minimize and evenly distribute the interconnects across the physical devices. Our experimental evaluation on the ISPD98 benchmark show that ouralgorithms produce solutions that when compared against thoseproduced by hMETIS have a maximum subdomain degree that isreduced by up to 35% while achieving comparable quality in terms of cut.