Field-programmable gate arrays
Field-programmable gate arrays
Placement and routing tools for the Triptych FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Emerald: an architecture-driven tool compiler for FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Proceedings of the 1997 international symposium on Physical design
Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
The design of an SRAM-based field-programmable gate array—part I: architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Detailed routing architectures for embedded programmable logic IP cores
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
FPGA switch block layout and evaluation
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Analysis of FPGA/FPIC switch modules
ACM Transactions on Design Automation of Electronic Systems (TODAES)
The stratixπ routing and logic architecture
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Testing Layered Interconnection Networks
IEEE Transactions on Computers
The Stratix II logic and routing architecture
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Design, layout and verification of an FPGA using automated tools
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Layout techniques for FPGA switch blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Routing architecture optimizations for high-density embedded programmable IP cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Automatic design of reconfigurable domain-specific flexible cores
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Reducing the cost of floating-point mantissa alignment and normalization in FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Selective flexibility: breaking the rigidity of datapath merging
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
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In this paper we present a “high-level” FPGA architecture description language which lets FPGA architects succinctly and quickly describe an FPGA routing architecture. We then present an “architecture generator” built into the VPR CAD tool [1, 2] that converts this high-level architecture description into a detailed and completely specified flat FPGA architecture. This flat architecture is the representation with which CAD optimization and visualization modules typically work. By allowing FPGA researchers to specify an architecture at a high-level, an architecture generator enables quick and easy “what-if” experimentation with a wide range of FPGA architectures. The net effect is a more fully optimized final FPGA architecture. In contrast, when FPGA architects are forced to use more traditional methods of describing an FPGA (such as the manual specification of every switch in the basic file of the FPGA), far less experimentation can be performed in the same time, and the architectures experimented upon are likely to be highly similar, leaving important parts of the design space completely unexplored.This paper describes the automated routing architecture generation problem, and highlights the two key difficulties — creating an FPGA architecture that matches all of an FPGA architect's specifications, while simultaneously determining good values for the many unspecified portions of an FPGA so that a high quality FPGA results. We describe the method by which we generate FPGA routing architectures automatically, and present several examples.