Tightly Integrated Placement and Routing for FPGAs
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Rapid and Reliable Routability Estimation for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
On Routing Demand and Congestion Estimation for FPGAs
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
Analysis of the Effect of LUT Size on FPGA Area and Delay Using Theoretical Derivations
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Congestion estimation and localization in fpgas:: a visual tool for interconnect prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
Integration of Net-Length Factor with Timing- and Routability-Driven Clustering Algorithms
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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This paper investigates the problem of routability prediction in a FPGA that employs a hierarchical routing architecture. Such a FPGcl is called a hierarchical FPGA(HFPGA). A novel model is proposed to analyze various HFPGA configurations. A software tool has been developed to predict the routability of circuits on specific HFPGx4 architectures. Primary contribution of this work is that routability prediction can be done immediately after the technology-mapping step, rather than after placement. The effect of connection block and switch block flexibility on routability is also studied. The results show that compared to a symmetrical FPGA architecture, we can achieve the same degree of routability on a HFPG-4, with much fewer routing switches