PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
FPGA routing and routability estimation via Boolean satisfiability
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
On the behavior of congestion minimization during placement
ISPD '99 Proceedings of the 1999 international symposium on Physical design
Interconnect complexity-aware FPGA placement using Rent's rule
Proceedings of the 2001 international workshop on System-level interconnect prediction
Estimating routing congestion using probabilistic analysis
Proceedings of the 2001 international symposium on Physical design
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Routability Prediction for Hierarchical FPGAs
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Performance-driven simultaneous placement and routing for FPGA's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
On metrics for comparing routability estimation methods for FPGAs
Proceedings of the 39th annual Design Automation Conference
Rapid and Reliable Routability Estimation for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
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Interconnection planning is becoming an important design issue for ASICs and large FPGAs. As the technology shrinks and the design density increases, proper planning of routing resources becomes all the more important to ensure rapid and feasible design convergence. One of the most important issues for planning interconnection is the ability to predict the routability of a given placed design. This paper provides insight into the workings of recently proposed method by Lou et. al.[Lou_Shankar] and compares it with our proposed methodology, fGREP[fGREP]. We have implemented the two methods for a generic FPGA architecture and compare the performance, accuracy and usability of their estimates. We use the well known FPGA physical design suite VPR[VPR], as a common comparison tool. Our experiments show that fGREP produces far better routing estimates but at larger execution times than Lou's method. Insight into what makes the methods work and where they falter are also discussed in detail.