On routability prediction for field-programmable gate arrays
DAC '93 Proceedings of the 30th international Design Automation Conference
RISA: accurate and efficient placement routability modeling
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
PathFinder: a negotiation-based performance-driven router for FPGAs
FPGA '95 Proceedings of the 1995 ACM third international symposium on Field-programmable gate arrays
FPGA routing and routability estimation via Boolean satisfiability
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
Trading quality for compile time: ultra-fast placement for FPGAs
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Routability Prediction for Hierarchical FPGAs
GLS '99 Proceedings of the Ninth Great Lakes Symposium on VLSI
Performance-driven simultaneous placement and routing for FPGA's
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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With increasing FPGA device capacity and design sizes, physical design closure is becoming more difficult, usually requiring multiple lengthy cycles of placement and routing. Increasing demands are being placed upon the placement method to produce routable solutions. Existing FPGA physical design methodologies treat placement and routing as two distinct steps resulting in significant loss of quality and increased design times. A tighter integration between placement and routing is expected to reduce the overall physical design time and produce better quality solutions. This paper presents a new methodology for tightly integrated placement and routing for FPGAs. It provides the capability to introduce the routing concepts to the placement stage itself, ensuring the placement is routability driven and that desired good routes exist for all nets, in the routing stage. This methodology has been implemented for XC6200 family of FPGAs, but can be used with any FPGA architecture.