Design of delay insensitive circuits using multi-ring structures

NULL Convention multiply and accumulate unit with conditional rounding, scaling, and saturation

Journal of Systems Architecture: the EUROMICRO Journal

Optimal Two-Level Delay - Insensitive Implementation of Logic Functions

PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation

Optimization of NULL convention self-timed circuits

Integration, the VLSI Journal

Design of a logic element for implementing an asynchronous FPGA

Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays

Automated energy calculation and estimation for delay-insensitive digital circuits

Microelectronics Journal

Design of an FPGA logic element for implementing asynchronous NULL convention logic circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Elastic circuits

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Dual-rail asynchronous logic multi-level implementation

Integration, the VLSI Journal