Design of a logic element for implementing an asynchronous FPGA

Authors:
Scott C. Smith
Affiliations:
University of Missouri - Rolla, Rolla, MO
Venue:
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Year:
2007

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Abstract

A reconfigurable logic element (LE) is developed for use in constructing a NULL Convention Logic (NCL) FPGA. It can be configured as any of the 27 fundamental NCL gates, including resettable and inverting variations, and can utilize embedded registration for gates with three or fewer inputs. The developed LE is compared with a previous NCL LE, showing that the one developed herein yields a more area efficient NCL circuit implementation. The NCL FPGA logic element is simulated at the transistor level using the 1.8V, 180nm TSMC CMOS process.