Design and characterization of NULL convention arithmetic logic units

Authors:
Satish K. Bandapati;Scott C. Smith
Affiliations:
University of Missouri - Rolla, Department of Electrical and Computer Engineering, 133 Emerson Electric Co. Hall, 1870 Miner Circle, Rolla, MO 65409, United States;University of Missouri - Rolla, Department of Electrical and Computer Engineering, 133 Emerson Electric Co. Hall, 1870 Miner Circle, Rolla, MO 65409, United States
Venue:
Microelectronic Engineering
Year:
2007

Citing 5
Cited 2

NULL Convention multiply and accumulate unit with conditional rounding, scaling, and saturation

Journal of Systems Architecture: the EUROMICRO Journal
NULL Convention Logic/sup TM/: A Complete And Consistent Logic For Asynchronous Digital Circuit Synthesis

ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Checking Delay-Insensitivity: 104 Gates and Beyond

ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Gate and throughput optimizations for null convention self-timed digital circuits

Gate and throughput optimizations for null convention self-timed digital circuits
Optimization of NULL convention self-timed circuits

Integration, the VLSI Journal

Design of a logic element for implementing an asynchronous FPGA

Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Design of an FPGA logic element for implementing asynchronous NULL convention logic circuits

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Quantified Score

Hi-index	2.88

Visualization

Abstract

In this paper, a number of 4-bit, 8-operation arithmetic logic units (ALUs) are designed using the delay-insensitive NULL convention logic paradigm, and are characterized in terms of speed and area. Both dual-rail and quad-rail, pipelined and non-pipelined versions are developed, and the tradeoffs and design considerations for each are discussed. Comparing the various architectures shows that the fastest dual-rail and quad-rail ALUs achieve average speedups of 1.72 and 1.59, respectively, over their non-pipelined counterparts, while requiring 133% and 119% more area, respectively. Overall, the dual-rail designs are both faster and require less area than their respective quad-rail counterparts; however, the quad-rail versions are expected to consume less power.