Optimal Two-Level Delay - Insensitive Implementation of Logic Functions

Authors:
Igor Lemberski;Mark B. Josephs
Affiliations:
-;-
Venue:
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Year:
2002

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Abstract

We proposed an approach to multi-output optimal two-level delay-insensitive (DI) implementation of logic functions. It bases on the procedure of logic minimization. We formulated and proved constraints the minimized logic implementation remains delay-insensitive for. Also, we pointed out an existing tool that produces result under constraints formulated. Using this tool we processed several examples and compared implementation complexity with one obtained using known approach. We achieved more than 4 times improvement.