An Efficient Implementation of Boolean Functions as Self-Timed Circuits
IEEE Transactions on Computers
Design of delay insensitive circuits using multi-ring structures
EURO-DAC '92 Proceedings of the conference on European design automation
NULL Convention multiply and accumulate unit with conditional rounding, scaling, and saturation
Journal of Systems Architecture: the EUROMICRO Journal
Optimization of NULL convention self-timed circuits
Integration, the VLSI Journal
Design of an FPGA logic element for implementing asynchronous NULL convention logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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This thesis presents a design methodology for self-timed systems which will be extremely attractive for implementing systems in VLSI. Self-timed systems are characterized by the absence of a timing reference to which all operations are synchronized. Currently most systems are implemented using a synchronous design methodology where all operations are synchronized to a global clock. However, this approach will not be attractive in the future for implementing systems in VLSI due to the high communications costs in VLSI and the prohibitive task of managing timing constraints global to a VLSI integrated circuit. The methodology proposed in this thesis defines a set of modules which form the building blocks for implementing an arbitrary self-timed system. The various module types are based on familiar programming constructs such as iterations, conditionals and constructs that aid in the activation and synchronization of parallel processes, such as, forking and joining. The modules of a self-timed system communicate with each other via an asynchronous communication protocol, and the correct behavior of the system is independent of the delays in the communication medium. This methodology simplifies the design effort by restricting the timing constraints to be local to the modules of the system.