DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Layout driven technology mapping
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Analytical placement: A linear or a quadratic objective function?
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Minimizing the routing cost during logic extraction
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Technology mapping for low power in logic synthesis
Integration, the VLSI Journal
Design of a logic synthesis system (tutorial)
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Physical design and synthesis (panel): merge or die!
DAC '97 Proceedings of the 34th annual Design Automation Conference
Logic extraction based on normalized netlengths
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Sequential Circuit Design Using Synthesis and Optimization
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Prediction of interconnect delay in logic synthesis
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Logic synthesis for vlsi design
Logic synthesis for vlsi design
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This paper presents a technology mapping approach for the standard cell technology, which takes into account both gate area and routing area so as to minimize the total chip area after layout. The routing area is estimated using two parameters available at the mapping stage; one is the fanout count of a gate, and the other is the "overlap of fanin level intervals". To estimate the routing area in terms of accurate fanout counts, an algorithm is proposed which solves the problem of dynamic fanout changes in the mapping process. This also enables us to calculate the gate area more accurately. Experimental results show that this approach provides an average reduction of 15% in the final chip area after placement and routing.