Clocking Schemes for High-Speed Digital Systems
IEEE Transactions on Computers
Aesop: a tool for automated transistor sizing
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Transistor sizing in CMOS circuits
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
Delay and power optimization in VLSI circuits
DAC '84 Proceedings of the 21st Design Automation Conference
Analytical power/timing optimization technique for digital system
DAC '77 Proceedings of the 14th Design Automation Conference
APT: an area-performance-testability driven placement algorithm
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
On the circuit implementation problem
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
A near optimal algorithm for technology mapping minimizing area under delay constraints
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Delay and area optimization for compact placement by gate resizing and relocation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
EURO-DAC '94 Proceedings of the conference on European design automation
Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
A unified algorithm for gate sizing and clock skew optimization to minimize sequential circuit area
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Gate sizing with controlled displacement
ISPD '99 Proceedings of the 1999 international symposium on Physical design
An exact gate assignment algorithm for tree circuits under rise and fall delays
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Timing driven gate duplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Upgrading arc problem with budget constraint
Proceedings of the 43rd annual Southeast regional conference - Volume 1
A new algorithm for simultaneous gate sizing and threshold voltage assignment
Proceedings of the 2009 international symposium on Physical design
Implementing and clustering modules with complex delays
Integration, the VLSI Journal
A new algorithm for simultaneous gate sizing and threshold voltage assignment
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Eyecharts: constructive benchmarking of gate sizing heuristics
Proceedings of the 47th Design Automation Conference
Gate sizing and device technology selection algorithms for high-performance industrial designs
Proceedings of the International Conference on Computer-Aided Design
An efficient algorithm for library-based cell-type selection in high-performance low-power designs
Proceedings of the International Conference on Computer-Aided Design
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We examine the problem of choosing the proper sizes from a cell library for the logic elements of a Boolean network to meet timing constraints on the propagation delay along every path from the primary input to the primary output. If the Boolean network has a tree topology, we show that there exists a pseudo-polynomial time algorithm for finding the optimal solution to this problem. A backtracking-based algorithm for finding feasible solutions for networks that are not trees is also suggested and evaluated.