Gate sizing and buffer insertion for optimizing performance in power constrained BiCMOS circuits

Authors:
Kerry S. Lowe;P. Glenn Gulak
Affiliations:
Department of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario, Canada M5S 1A4;Department of Electrical and Computer Engineering, University of Toronto, Toronto, Ontario, Canada M5S 1A4
Venue:
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Year:
1993

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Abstract