Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Technology mapping for electrically programmable gate arrays
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Performance-oriented technology mapping
Performance-oriented technology mapping
Boolean matching in logic synthesis
EURO-DAC '92 Proceedings of the conference on European design automation
Efficient Boolean function matching
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
SOCRATES: a system for automatically synthesizing and optimizing combinational logic
DAC '86 Proceedings of the 23rd ACM/IEEE Design Automation Conference
Logic synthesis for vlsi design
Logic synthesis for vlsi design
LSS: a system for production logic synthesis
IBM Journal of Research and Development
Fast Boolean Matching with Don't Cares
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
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We present an improved method for technology mapping using a new approach to the Boolean matching problem. Signatures computed over OBDDs using a set of specific probability values determine matches between library cells and portions of the netlist. Unlike some previous methods, which may require creation of up to O(n!) OBDDs for all possible permutations of module's inputs, our method requires exactly one OBDD to be created for the portion of the netlist being matched. Some results obtained on ISCAS85 benchmark circuits suggest the viability and validity of our approach.