DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Characterization of Boolean functions for rapid matching in FPGA technology mapping
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Boolean matching for incompletely specified functions
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Data Structures and Algorithms
Data Structures and Algorithms
LSS: a system for production logic synthesis
IBM Journal of Research and Development
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Ending the logic synthesis, the technology mapping step maps the Boolean function on physical cells. This itep is based on a matching check, which complexity depends on the number of library cell inputs, and increases if don't cares are considered. The method presented here is based on fault analysis. Using a structural equivalent of the cell, it allows to prune dramatically the design space, and derives at the same time the input phase. The experimental results show a real improvement in CPU time compared to ROBDD based Boolean matching, and are promising to handle complex cells.