The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
Introduction to VLSI Systems
Switch-level delay models for digital MOS VLSI
DAC '84 Proceedings of the 21st Design Automation Conference
Analytical power/timing optimization technique for digital system
DAC '77 Proceedings of the 14th Design Automation Conference
Signal Delay in RC Tree Networks
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Switch-Level Timing Verifier for Digital MOS VLSI
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Synthesis and Optimization of Multilevel Logic under Timing Constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Macromodeling and Optimization of Digital MOS VLSI Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Network Partitioning and Ordering for MOS VLSI Circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
CMOS Circuit Speed and Buffer Optimization
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Gate sizing for large cell-based designs
Proceedings of the Conference on Design, Automation and Test in Europe
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This article describes a new method to determine the device sizes of combinational digital CMOS circuits for an upper limit on the signal propagation delays. By modeling gate delay and area or power consumption of a circuit as a simple analytical function of the device sizes, transistor sizing can be stated as a standard nonlinear program. A new and efficient problem formulation with a complexity proportional to the circuit size is presented that allows the optimization of large circuits with reasonable effort. During the optimization a sequence of valid and improved circuit configurations is produced such that the optimization may be stopped prematurely while comparing different implementation alternatives.