DAGON: technology binding and local optimization by DAG matching
DAC '87 Proceedings of the 24th ACM/IEEE Design Automation Conference
IEEE Spectrum
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
An architecture for synthesis of testable finite state machines
EURO-DAC '90 Proceedings of the conference on European design automation
Simplifying Sequential Circuit Test Generation
IEEE Design & Test
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We present a new synthesis for testability method in which a test function is incorporated into the state diagram of the finite state machine (FSM). The test function is specified as a FSM with the same number of state variables as the given object machine. The state graph of the test machine is so defined that each state is uniquely set and observed by an input sequence no longer than ⌈logkn⌉, where n is the number of states and the integer k is a design parameter. The state transition graph of the test machine is superimposed on the state graph of the object function such that a minimal number of new transitions are added. State assignment, logic minimization and technology mapping are then carried out for the combined graph. By design, the embedded test machine is fully testable. Also, since the test machine can control all memory elements, the circuit is effectively tested by a combinational circuit test generator. Scan register is shown to be a special case in this methodology.