Wire length prediction-based technology mapping and fanout optimization

Authors:
Qinghua Liu;Malgorzata Marek-Sadowska
Affiliations:
University of California, Santa Barbara, CA;University of California, Santa Barbara, CA
Venue:
Proceedings of the 2005 international symposium on Physical design
Year:
2005

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Abstract

In modern VLSI systems early wire optimization is essential in achieving required performance, routability, and power. The cost functions optimized during traditional logic synthesis do not capture interconnect effects, which may lead to sub-optimal designs. In this paper, we propose a method for applying pre-layout wire-length prediction techniques in logic synthesis, targeting wiring cost and ways to minimize congestion. Specifically, we focus on technology mapping and fanout optimization. Experimental results show that our wire-length-prediction-based technology mapping (WP-Map) and fanout optimization (WP-Fanout) result in 8.7% improvement in average congestion, 17.2% improvement in peak congestion, and 3.3% improvement in timing performance.