Layout-aware gate duplication and buffer insertion

Authors:
D. Bañeres;J. Cortadella;M. Kishinevsky
Affiliations:
Universitat Politècnica de Catalunya, Barcelona, Spain;Universitat Politècnica de Catalunya, Barcelona, Spain;Strategic CAD Lab, Intel Corp., Hillsboro, OR
Venue:
Proceedings of the conference on Design, automation and test in Europe
Year:
2007

Citing 18
Cited 1

Performance-oriented technology mapping

AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
A heuristic algorithm for the fanout problem

DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Performance-driven interconnect design based on distributed RC delay model

DAC '93 Proceedings of the 30th international Design Automation Conference
Optimal wire sizing and buffer insertion for low power and a generalized delay model

ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
New performance driven routing techniques with explicit area/delay tradeoff and simultaneous wire sizing

DAC '96 Proceedings of the 33rd annual Design Automation Conference
Buffered Steiner tree construction with wire sizing for interconnect layout optimization

Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
A simultaneous routing tree construction and fanout optimization algorithm

Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Efficient global fanout optimization algorithms

Proceedings of the 2001 Asia and South Pacific Design Automation Conference
A new algorithm for routing tree construction with buffer insertion and wire sizing under obstacle constraints

Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
An Efficient k-Means Clustering Algorithm: Analysis and Implementation

IEEE Transactions on Pattern Analysis and Machine Intelligence
A fast algorithm for identifying good buffer insertion candidate locations

Proceedings of the 2004 international symposium on Physical design
Timing driven gate duplication

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Simultaneous timing-driven placement and duplication

Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Wire length prediction-based technology mapping and fanout optimization

Proceedings of the 2005 international symposium on Physical design
Techniques for improved placement-coupled logic replication

GLSVLSI '06 Proceedings of the 16th ACM Great Lakes symposium on VLSI
On the complexity of gate duplication

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
FastPlace: efficient analytical placement using cell shifting, iterative local refinement,and a hybrid net model

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A fast algorithm for optimal buffer insertion

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems

Ultra-fast interconnect driven cell cloning for minimizing critical path delay

Proceedings of the 19th international symposium on Physical design

Quantified Score

Hi-index	0.00

Visualization

Abstract

An approach for layout-aware interconnect optimization is presented. It is based on the combination of three sub-problems into the same framework: gate duplication, buffer insertion and placement. Different techniques to control the combinatorial explosion are proposed. The experimental results show tangible benefits in delay that endorse the suitability of integrating the three sub-problems in the same framework. The results also corroborate the increasing relevance of interconnect optimization in future semiconductor technologies.