Alphabetic minimax trees of degree atmost t
SIAM Journal on Computing
Concrete mathematics: a foundation for computer science
Concrete mathematics: a foundation for computer science
The fanout problem: from theory to practice
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Performance-oriented technology mapping
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
A heuristic algorithm for the fanout problem
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Layout driven technology mapping
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Performance-oriented technology mapping
Performance-oriented technology mapping
Bounding Fan-out in Logical Networks
Journal of the ACM (JACM)
Graph Algorithms
The Art of Computer Programming, 2nd Ed. (Addison-Wesley Series in Computer Science and Information
The Art of Computer Programming, 2nd Ed. (Addison-Wesley Series in Computer Science and Information
A methodology and algorithms for post-placement delay optimization
DAC '94 Proceedings of the 31st annual Design Automation Conference
Minimal delay interconnect design using alphabetic trees
DAC '94 Proceedings of the 31st annual Design Automation Conference
Minimizing the routing cost during logic extraction
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Delay optimal partitioning targeting low power VLSI circuits
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Post-layout optimization for deep submicron design
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Buffered Steiner tree construction with wire sizing for interconnect layout optimization
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Delay bounded buffered tree construction for timing driven floorplanning
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Timing driven placement in interaction with netlist transformations
Proceedings of the 1997 international symposium on Physical design
Wireplanning in logic synthesis
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Fanout optimization under a submicron transistor-level delay model
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Performance optimization under rise and fall parameters
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Layout-driven area-constrained timing optimization by net buffering
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
An exact gate assignment algorithm for tree circuits under rise and fall delays
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Timing driven gate duplication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wire length prediction-based technology mapping and fanout optimization
Proceedings of the 2005 international symposium on Physical design
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