Delay optimal partitioning targeting low power VLSI circuits

Authors:
Hirendu Vaishnav;Massoud Pedram
Affiliations:
University of Southern California, Department of Electrical Engineering Systems, Los Angeles, CA;University of Southern California, Department of Electrical Engineering Systems, Los Angeles, CA
Venue:
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Year:
1995

Citing 4
Cited 4

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Abstract

Abstract: In this paper, a delay optimal clustering/partitioning algorithm for minimizing the power dissipation of a circuit is proposed. Traditional approaches for delay optimal partitioning are based on Lawler's clustering algorithm that makes no attempt to explore alternative partitioning solutions that have the same delay but better power implementations. Our algorithm provides a formal mechanism which implicitly enumerates alternate partitionings and selects a partitioning that has the same delay but less power dissipation. For tree circuits, the proposed algorithm produces delay and power optimal partitioning whereas for non-tree circuits it produces delay optimal partitioning with significantly improved power dissipation.