Minimal delay interconnect design using alphabetic trees

  • Authors:
  • Ashok Vittal;Malgorzata Marek-Sadowska

  • Affiliations:
  • Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA;Department of Electrical and Computer Engineering, University of California, Santa Barbara, CA

  • Venue:
  • DAC '94 Proceedings of the 31st annual Design Automation Conference
  • Year:
  • 1994

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Abstract